Dr. Janhavi Giri

Dr. Janhavi Giri

Principal Architect & Technical Industry Lead

Semiconductor EDA Strategy | NetApp

IEEE CAS Industrial Distinguished Lecturer Circuits & Systems Society · Term 2026–2027

AI Infrastructure • GPU-Accelerated EDA • Manufacturing Analytics

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About

I operate at the intersection of semiconductor engineering, AI systems, and data infrastructure, helping teams move advanced AI from experimentation into production-scale deployment.

As Principal Architect and Technical Industry Lead for Semiconductor EDA Strategy at NetApp, I focus on end-to-end platforms spanning design, manufacturing, and ecosystem workflows. My work emphasizes GPU-accelerated EDA, manufacturing analytics, and AI-ready data infrastructure—connecting technical depth with business impact.

I am an active industry speaker and technical leader, with a long-term focus on building scalable, ecosystem-level AI platforms for the semiconductor industry.

As the field evolves, I remain passionate about building partnerships that accelerate AI and high-performance computing adoption across design, EDA, and manufacturing.

Education

Ph.D.

University of Illinois at Chicago, USA

M.S. Applied Mathematics

University of Bristol, UK

M.S. Physics

M.L.S University, India

Top Skills

Semiconductors Data Science Program Management People Management Cross-functional Leadership

Professional Experience

NetApp

NetApp

2025 - Present

Principal Architect & Technical Industry Lead

Semiconductor EDA Strategy

  • Leading end-to-end platform strategy spanning design, manufacturing, and ecosystem workflows
  • Driving GPU-accelerated EDA infrastructure and AI-ready data platforms
  • Building scalable, ecosystem-level AI platforms for semiconductor industry
  • Connecting technical depth with business impact across the semiconductor value chain
Intel

Intel Corporation

2012 - 2025

AI/ML Architect & Technical Lead

Foundry Automation, Technology Development & Manufacturing | Aug 2023 - Sep 2025

  • Architected and deployed end-to-end AI system for robotic inspection using Deep-TDA, resulting in $5.2M cost savings
  • Designed hybrid Deep-TDA + Causal AI framework to uncover equipment-driven yield loss mechanisms
  • Led PoC-to-production roadmap for CSAM and CDSEM image analytics

AI/ML Program Lead (Data Science Manager)

Central Manufacturing, NAND-DTM | Oct 2021 - Aug 2023

  • Directed team of data scientists focusing on AI/ML technologies for advanced data mining
  • Achieved cost-saving successes through Deep-TDA and causal graphs
  • Developed wafer map image analysis for defect detection

RET/ILT Technologist

Memory & Logic Technology Development | 2012 - 2021

  • Delivered high-quality OPC solutions for 3D NAND and Optane Memory products
  • Contributed to Moore's law advancement across four microprocessor generations (22nm-7nm)
  • Implemented advanced RET, ILT, and Source Mask Optimization
Siemens EDA

Siemens EDA (Mentor Graphics)

2016 - 2017

Technical Team Lead

Software Qualification & Verification, Calibre RET

  • Led team for qualification of RET products (SRAF, EUV nmOPC, EUV OPCVerify)
  • Developed automation tools to improve QA process efficiency
  • Ensured test coverage aligned with semiconductor manufacturing flows

Domain Expertise

Semiconductor Domain

  • Full design-to-silicon flow: tape-in → layout synthesis → OPC → verification → tapeout → mask manufacturing → fab qualification
  • Semiconductor process: multi-patterning & self-aligned vias, DUV (dry/immersion) & EUV lithography, yield ramp-up, NPIs, scribe design
  • EDA/RET tapeout tools: Mentor Calibre RET & MDP, Synopsys Proteus RET, ILT, ProGen, IC Validator; ASML SMO; Cadence KLayout

AI/ML Domain

  • Classical ML: XGBoost, LightGBM, Scikit-learn
  • Deep Learning: CNNs, Transformers, GANs, VAEs (PyTorch, TensorFlow, Keras)
  • Generative AI & LLMs: prompt engineering, RAG, AI agents & orchestration
  • ML lifecycle: problem scoping, rapid prototyping, validation, deployment & monitoring (MLflow, Weights & Biases)
  • Ecosystem & tooling: Python, SQL, Git, Databricks, Pandas, NumPy, NVIDIA RAPIDS, CUDA-X, ONNX

Topological Data Analysis

Deep TDA for semiconductor image analytics, defect detection, and pattern recognition using persistent homology and mapper algorithms.

Causal AI

Causal inference frameworks using boosting trees for root cause analysis and equipment-driven yield loss identification.

GPU-Accelerated EDA

High-performance computing infrastructure for AI-driven design automation and manufacturing analytics at scale.

Publications & Articles

Research Publications

182 citations | h-index: 5
View Full Profile on Google Scholar

Advanced Clustering Framework for Semiconductor Image Analytics Integrating Deep TDA with Self-Supervised and Transfer Learning Techniques

J Giri, A Lengyel, D Kent, E Kibardin

arXiv preprint arXiv:2505.03848, 2025

1 citation

Explainable machine learning approach to yield and quality improvements using deep topological data analytics

J Giri, A Lengyel

International Electronic Packaging Technical Conference and Exhibition, 2023

Best Paper Nominee

6 citations

Invited Talks & Presentations

2026

From Copilots to AI Factories: The Data Infrastructure Gap Blocking Autonomous Semiconductor Manufacturing

INEMI Smart Manufacturing Tech Topic Series

May 7, 2026  |  Webinar

Invited Talk

Agentic AI for Semiconductor Design and Manufacturing: From Wafer Data Workflows to Intelligent EDA Systems

BETR/EECS Solid State Technologies Seminar, UC Berkeley

March 13, 2026  |  Hogan Room, Cory Hall, UC Berkeley

Invited Seminar

Agentic AI for Semiconductor Design and Manufacturing

NVIDIA GTC 2026 — NetApp

March 17, 2026  |  San Jose, CA

Conference Talk

Beyond Moore's Law: The Future of Semiconductor Manufacturing Intelligence

SemiWiki Webinar — NetApp (EDA & Semiconductor Industry Vertical Lead)

April 23, 2026  |  Webinar

Webinar

2025

Agentic AI and Topological Data Analysis for Semiconductor Industry

Applied Materials — ET Guest Lecture Series

October 2025  |  Invited Lecture

Guest Lecture

Agentic AI & The Future of EDA Infrastructure — Panel Discussion

SemiWiki Webinar — NetApp & Cadence (with Rob Knoth, Cadence; Khaled Heloue, AMD; moderated by Daniel Nenni, SemiWiki)

December 4, 2025  |  Webinar

Panel

Enhancing Yield and Quality with Explainable AI

INEMI Smart Manufacturing Tech Topic Series

May 6, 2025  |  Webinar

Invited Talk

From Data to Decisions: A Hands-On Tutorial in Agentic AI

IEEE Bangalore Technology Conference (BTC 2025) — Tutorial 7

2025  |  Bangalore, India

Tutorial

Deep Topological Data Analysis and Self-Supervised Learning for Yield and Quality Optimization

IEEE Symposium on VLSI Technology and Circuits 2025 — Workshop 3: Semiconductor Manufacturing with AI

2025  |  IEEE VLSI Symposium

Workshop Talk

2024

Deep Topological Data Analysis and Self-Supervised Learning for Semiconductor Image Analytics

SEMICON West 2024 — Smart Manufacturing Pavilion Stage

July 9, 2024, 2:30–2:50 PM PDT  |  San Francisco, CA

Invited Talk

2023

Explainable Machine Learning Approach to Yield and Quality Improvements Using Deep Topological Data Analytics

ASME InterPACK 2023 — International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems

October 24–26, 2023  |  San Diego, CA  |  Published: DOI 10.1115/IPACK2023-111525

Invited Talk & Published

Advancing Root Cause Analysis With Causal Inference Using Boosting Trees And Topological Data Analysis

INFORMS Annual Meeting 2023

October 15–18, 2023  |  Phoenix, AZ

Conference Talk

Recognition & Media Coverage

Featured Honor Term 2026–2027

IEEE CAS Industrial Distinguished Lecturer

IEEE Circuits and Systems Society — one of the most prestigious recognitions in the circuits and systems field, awarded to industry leaders who advance the discipline through distinguished lectures worldwide.

Lecture Topics: Intelligent Memory & Storage for AI-Driven EDA · Deep Topological Data Analysis for IC Data · Agentic AI for Semiconductor Design & Manufacturing

SPIE Women in Optics

Featured by SPIE - The International Society for Optics and Photonics in their Women in Optics recognition program (2019)

Media Coverage - Indica News

Featured at SEMICON West 2024 discussing self-teaching machines and AI's promise in semiconductor manufacturing

Best of LinkedIn - Smart Manufacturing

Featured in Best of LinkedIn Posts on Smart Manufacturing; highlighted as a key industry voice to follow (minute 2:13)

Intel Technology Awards

Multiple Intel Technology Development Divisional Awards for OPC solutions and semiconductor yield improvements

Best Paper Nominee

Nominated for Best Paper at ASME InterPACK2023 for work on explainable ML and Deep TDA

Industry Recognition

Recognized for sustained technical leadership and knowledge dissemination in Topological Data Analysis

Open Source Projects

Get In Touch

I am always interested in connecting with researchers, industry professionals, and organizations working on cutting-edge problems in semiconductor manufacturing, AI/ML, and related fields. Whether you're looking for collaboration, consultation, or speaking opportunities, feel free to reach out.

Location

San Francisco Bay Area, CA, USA